IP Registry

High-performance SHA-256 hash engine with AXI4-Stream interface. Optimized for streaming data with configurable pipeline depth.

Flexible AXI4 crossbar interconnect with configurable ports and arbitration. Supports up to 16 masters and 16 slaves.

Compact UART controller with APB interface. Configurable baud rate, parity, and FIFO depth. Ideal for embedded systems.

Parameterized FIR filter with configurable taps and coefficients. Supports fixed-point and floating-point arithmetic.

PCIe Gen3 DMA engine with scatter-gather support. Experimental release targeting high-bandwidth data transfer applications.

Compact RISC-V RV32IM core with 5-stage pipeline. Optimized for area efficiency in embedded applications.

DDR4 memory controller with AXI4 interface. Supports multiple ranks and ECC. Currently in beta testing.

HDMI 2.0 transmitter with video timing generator. Supports up to 4K@60Hz with HDR metadata passthrough.