mem.ctrl.ddr4

beta

v2.0.0-beta

Author: Memory Systems Inc

License: Proprietary

DDR4 memory controller with AXI4 interface. Supports multiple ranks and ECC. Currently in beta testing.

Interfaces

Name	Type	Role	Width
s_axi	AXI4	slave	512
ddr4	DDR4	controller	72

Parameters

Name	Type	Default	Constraints
DATA_WIDTH	integer	64	32, 64
ECC_ENABLE	boolean	true	-
NUM_RANKS	integer	1	1, 2, 4
REFRESH_MODE	string	AUTO	AUTO, MANUAL

Compatibility

Clock Domains

AXI clock
DDR4 clock (1.2 GHz)

Reset Semantics

Asynchronous active-low reset

Tool Support

Vivado 2023.2+Quartus 23.4+

Verification

Tests

Read/write patterns
ECC injection
Stress tests

Simulators

VCSQuesta

Coverage

85% functional coverage

Build Proof

Target	Tool	Status	Fmax	Resources
Xilinx Kintex UltraScale+	Vivado 2023.2	Pass	300 MHz	12,400 LUTs
Intel Stratix 10	Quartus 23.4	Pass	320 MHz	14,200 ALMs

Manifest

ip.yaml

name: mem.ctrl.ddr4
version: 2.0.0-beta
license: Proprietary
author: Memory Systems Inc

description: >
  DDR4 memory controller with AXI4 interface.
  Supports multiple ranks and ECC.

interfaces:
  s_axi:
    type: axi4
    role: slave
    width: 512
  ddr4:
    type: ddr4
    role: controller
    width: 72

parameters:
  DATA_WIDTH:
    type: integer
    default: 64
    values: [32, 64]
  ECC_ENABLE:
    type: boolean
    default: true
  NUM_RANKS:
    type: integer
    default: 1
    values: [1, 2, 4]

targets:
  - vivado
  - quartus