silicon.apb.uart

stable

v1.0.3

Author: Silicon Commons

License: BSD-3-Clause

Compact UART controller with APB interface. Configurable baud rate, parity, and FIFO depth. Ideal for embedded systems.

Interfaces

Name	Type	Role	Width
apb	APB	slave	32
uart_tx	UART	master	1
uart_rx	UART	slave	1

Parameters

Name	Type	Default	Constraints
FIFO_DEPTH	integer	16	4, 8, 16, 32
DEFAULT_BAUD	integer	115200	-
CLK_FREQ_HZ	integer	100000000	-

Compatibility

Clock Domains

Single clock domain

Reset Semantics

Synchronous active-high reset

Tool Support

Vivado 2021.1+Yosys 0.30+OpenLane 2.0+

Verification

Tests

Loopback tests
Baud rate accuracy
FIFO overflow/underflow

Simulators

VerilatorIcarus VerilogCocotb

Coverage

91% line coverage

Build Proof

Target	Tool	Status	Fmax	Resources
Xilinx Artix-7	Vivado 2023.2	Pass	200 MHz	312 LUTs
Lattice ECP5	Yosys	Pass	125 MHz	428 LCs
Sky130	OpenLane	Pass	50 MHz	1,842 cells

Manifest

ip.yaml

name: silicon.apb.uart
version: 1.0.3
license: BSD-3-Clause
author: Silicon Commons

description: >
  Compact UART controller with APB interface.

interfaces:
  apb:
    type: apb
    role: slave
    width: 32
  uart_tx:
    type: uart
    role: master
  uart_rx:
    type: uart
    role: slave

parameters:
  FIFO_DEPTH:
    type: integer
    default: 16
    values: [4, 8, 16, 32]
  DEFAULT_BAUD:
    type: integer
    default: 115200

targets:
  - vivado
  - yosys
  - sky130