core.riscv.rv32im

beta

v1.2.0

Author: Open Core Initiative

License: MIT

Compact RISC-V RV32IM core with 5-stage pipeline. Optimized for area efficiency in embedded applications.

Interfaces

Name	Type	Role	Width
imem	AXI-Lite	master	32
dmem	AXI-Lite	master	32
wb_periph	Wishbone	master	32

Parameters

Name	Type	Default	Constraints
RESET_VECTOR	hex	0x00000000	-
ICACHE_SIZE	integer	4096	0, 1024, 2048, 4096, 8192
DCACHE_SIZE	integer	4096	0, 1024, 2048, 4096, 8192

Compatibility

Clock Domains

Single clock domain

Reset Semantics

Synchronous active-low reset

Tool Support

Vivado 2022.1+Yosys 0.32+OpenLane 2.0+

Verification

Tests

RISC-V compliance tests
riscv-tests suite
Dhrystone benchmark

Simulators

VerilatorSpike

Coverage

89% instruction coverage

Build Proof

Target	Tool	Status	Fmax	Resources
Xilinx Artix-7	Vivado 2023.2	Pass	100 MHz	3,200 LUTs
Lattice ECP5	Yosys	Pass	65 MHz	4,100 LCs
Sky130	OpenLane	Pass	25 MHz	28,500 cells

Manifest

ip.yaml

name: core.riscv.rv32im
version: 1.2.0
license: MIT
author: Open Core Initiative

description: >
  Compact RISC-V RV32IM core with 5-stage
  pipeline. Area-optimized.

interfaces:
  imem:
    type: axi-lite
    role: master
    width: 32
  dmem:
    type: axi-lite
    role: master
    width: 32
  wb_periph:
    type: wishbone
    role: master

parameters:
  RESET_VECTOR:
    type: hex
    default: "0x00000000"
  ICACHE_SIZE:
    type: integer
    default: 4096
    values: [0, 1024, 2048, 4096, 8192]

targets:
  - vivado
  - yosys
  - sky130